As feature densities in semiconductor devices increase, the widths of the conductive lines, and the spacing between the conductive lines of back-end of line (BEOL) interconnect structures in the semiconductor devices also need to be scaled down. Interconnects are often formed using damascene processes rather than by direct etching. Damascene processes are typically either single or dual damascene, which include forming openings by patterning and etching inter-metal dielectric (IMD) layers and filling the openings with a conductive material. However, there are some challenges in the damascene structure, such as double or triple patterning processes may be used and IMD layers may be exposed to wet chemicals and, therefore, result in damage of the IMD layers and device performance degradation. In particular, porous low-k IMD layers may suffer from solvent penetration into the IMD layer when exposed to wet chemicals. In addition, residuals from the ashing of overlying resist layers during resist layer removal can damage IMD layers. The ashing of overlying resist layers during resist layer removal can also damage IMD layers.